// +FHDR------------------------------------------------------------
//                 Copyright (c) 2024 NOVAUTO.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : async_pulse_widen.v
// Author        : ICer
// Created On    : 2024-03-14 14:06
// Last Modified : 2024-03-14 14:29 by ICer
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------


module async_pulse_widen #(
  parameter TIMES = 2
)( /*AUTOARG*/
   // Outputs
   o_data,
   // Inputs
   clk, rst_n, i_data
   );

// ----------------------------------------------------------------
// Interface declare
// ----------------------------------------------------------------
input  clk;
input  rst_n;
input  i_data;
output o_data;

// ----------------------------------------------------------------
// Wire declare
// ----------------------------------------------------------------
localparam TIMES_W = 8;

// ----------------------------------------------------------------
// AUTO declare
// ----------------------------------------------------------------
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/

reg  [TIMES_W -1:0]widen_cnt;
wire [TIMES_W -1:0]widen_cnt_d;
wire               widen_cnt_en;

assign widen_cnt_en = (i_data && widen_cnt == {TIMES_W{1'b0}}) ||
                      (widen_cnt == TIMES) ||
                      (widen_cnt != {TIMES_W{1'b0}}) ;

assign widen_cnt_d  = (i_data && widen_cnt == {TIMES_W{1'b0}}) ? widen_cnt + 1'b1 :
                      (widen_cnt == TIMES)                   ? 1'b0 :
                                                               widen_cnt + 1'b1;


always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    widen_cnt <= {TIMES_W{1'b0}};
  end
  else if(widen_cnt_en) begin
    widen_cnt <= widen_cnt_d;
  end
end

assign o_data = (widen_cnt != {TIMES_W{1'b0}});

endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:

